1. Field of Invention
The present invention relates to a method for manufacturing DRAM capacitors. More particularly, the present invention relates to the method of manufacturing high-density DRAM capacitors.
2. Description of Related Art
Dynamic random access memories (DRAMs) are now extensively used in integrated circuit devices. As electronic industries continue to flourish, higher capacity DRAMs are in great demand. Therefore, high-density capacitors are constantly researched and developed.
DRAMs use an array of capacitors fabricated on a semiconductor substrate to store digital data. In general, the charge storage states are utilized to store a bit of data. Normally, a capacitor capable of discharging is regarded as in a logic "1" state, and a capacitor that need charging is regarded as in a logic "0" state. Hence, a single bit of binary data is stored in a capacitor.
The charge storage capacity of a capacitor depends on several factors including surface area within the electrode of a capacitor, the reliability of the electrode isolation and the dielectric constant of the dielectric layer between the electrodes of a capacitor. Storage and retrieval of data to and from memory as well as reading and writing operations are executed by the transfer of charges to or from the capacitor and passed through a transfer field effect transistor (FET) via a coupled bit line. The bit line is connected to one source/drain terminal of the transfer FET, while the charge storage capacitor is connected to the other source/drain terminal of the transfer FET.
The gate of the transfer FET is connected to a word line. Control signals can then be sent through the word line to the gate of the transfer FET, thereby switching the transistor on. Hence, electrical connection between one electrode of the capacitor and the bit line is established, and the transfer of charges to and from the capacitor is allowed.
As the density of memory cells in an integrated circuit is increased, the relative cost for producing each bit of storage will decrease. In general, the density of an integrated circuit device can be increased by: (1) reducing the structural dimensions such as shortening wiring lines and decreasing the width of transistor gate; (2) reducing the distance between adjacent integrated circuit devices. Generally, a reduction in the structural dimensions means reducing the device dimensions in an integrated circuit. However, to reduce the device dimensions while maintaining certain basic functions, layouts, designs and any modifications must be adhered to a set of design rules.
A number of problems will be produced when the design rules for building smaller DRAM devices are followed. For example, as the charge storage capacity of a DRAM capacitor becomes too small, a minimum number of charges cannot be maintained within the capacitor. Under such circumstances, reading from the DRAM cell will be prone to errors.
Moreover, the data stored in the DRAM cell will be very weak in resisting external noises or a leakage in current. Consequently, the data residing in the DRAM cell needs to be refreshed frequently. Hence, DRAM capacitors that has a larger charge storage capacity within the confining, surface area of a given wafer is in great demand in the semiconductor industry.
In the conventional method of manufacturing DRAM capacitor, conventional photolithographic and etching techniques are generally used in defining, the lower electrode of a capacitor. Most often in photolithographic process, resolution is limited by the light source. Therefore, the lower electrodes of adjacent capacitors cannot be brought too near. Consequently, usable surface area for the capacitor cannot be increased, and so the capacitance of a capacitor cannot be increased.
In light of the foregoing, there is a need to improve the method of manufacturing a collection of DRAM capacitors.